LSM6DSTX datasheet(84/175 Pages) STMICROELECTRONICS

84 / 175 page

9.61

UI_INT_OIS (6Fh)

Enable setting of OIS interrupt configuration and accelerometer self-test register. The primary interface can write

this register when the OIS_CTRL_FROM_UI bit in the FUNC_CFG_ACCESS (01h) register is equal to 1 (primary

IF full-control mode). This register is read-only when the OIS_CTRL_FROM_UI bit is equal to 0 (SPI2 full-control

mode) and shows the content of the SPI2_INT_OIS (6Fh) register.

Table 163. UI_INT_OIS register

INT2_

DRDY_OIS

LVL2_OIS

DEN_LH_OIS

0(1)

SPI2_

READ_EN

0(1)

1. This bit must be set to 0 for the correct operation of the device.

Table 164. UI_INT_OIS register description

INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.

LVL2_OIS

Enables level-sensitive latched mode on the OIS chain. Default value: 0

DEN_LH_OIS

Indicates polarity of DEN signal on OIS chain

(0: DEN pin is active-low; 1: DEN pin is active-high)

SPI2_READ_EN

In primary IF full-control mode, enables auxiliary SPI for reading OIS data in registers

SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h) through SPI2_OUTZ_L_A_OIS (2Ch) and

SPI2_OUTZ_H_A_OIS (2Dh). Default value: 0

(0: reading OIS data from auxiliary SPI disabled;

1: reading OIS data from auxiliary SPI enabled)

LSM6DSTX

UI_INT_OIS (6Fh)

DS14039 - Rev 1

page 84/175

LSM6DSTX 数据表(PDF) 84 Page - STMicroelectronics