C5C5EDELTA-RMSLASHD datasheet(27/114 Pages) NXP

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C5C5EDELTA-RM/D 数据表(PDF) 27 Page - NXP Semiconductors

部件名	C5C5EDELTA-RM/D

功能描述	C-5e NETWORK PROCESSOR SILICON REVISION A1

PDF	114 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

标志

27 / 114 page

C5ENPA1-DS/D

Rev 03

Chapter 2

SIGNAL DESCRIPTIONS

Signal Summary

There are ten (10) functional groupings of signals in the C-5e Network Processor:

• Clock — 11 pins

• Channel Processors (CP0 - CP15) — 16x7 = 112 pins

• Executive Processor (XP) — 57 pins

– PCI Interface — 50 pins

– PROM Interface — 4 pins

– Serial Bus Interface — 2 pins

– General System Interface — 1 pin

• Fabric Processor (FP) — 80 pins

• Buffer Management Unit (BMU) — 160 pins

• Table Lookup Unit (TLU) — 99 pins

• Queue Management Unit (QMU) — 59 pins

• Power — 245 pins

• Test — 14 pins

• No connection (NC) — 3 pins

Two (2) of the sections (CPs and FP) are configurable, depending on the type of device

being implemented.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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