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C5C5EDELTA-RM/D 数据表(PDF) 37 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 37 Page - NXP Semiconductors |
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37 / 114 page ![]() Pin Descriptions Grouped by Function 37 03 CPn+1_0 Table 7 1 nc nc PD nc nc CPn+1_1 Table 7 1 LVTTL I PU COL Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation. CPn+1_2 Table 7 1 LVTTL O PD TXD(4) Transmit Data CPn+1_3 Table 7 1 LVTTL O PU TXD(5) Transmit Data CPn+1_4 Table 7 1 LVTTL O PD TXD(6) Transmit Data CPn+1_5 Table 7 1 LVTTL O PU TXD(7) Transmit Data (byte-wide receive data, most significant bit) CPn+1_6 Table 7 1 LVTTL O PU TX_ER Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated “bad code” in lieu of the normal encoded data on the twisted pair data. CPn+2_0 Table 7 1 nc nc PD nc nc CPn+2_1 Table 7 1 LVTTL IPU RCLK Receive Clock (125MHz) CPn+2_2 Table 7 1 LVTTL I PD RXD(0) Receive Data (byte-wide receive data, least significant bit) CPn+2_3 Table 7 1 LVTTL I PU RXD(1) Receive Data CPn+2_4 Table 7 1 LVTTL IPD RXD(2) Receive Data CPn+2_5 Table 7 1 LVTTL I PU RXD(3) Receive Data CPn+2_6 Table 7 1 LVTTL I PU RX_DV Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid. CPn+3_0 Table 7 1 nc nc PD nc nc CPn+3_1 Table 7 1 LVTTL I PU CRS Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected. CPn+3_2 Table 7 1 LVTTL I PD RXD(4) Receive Data CPn+3_3 Table 7 1 LVTTL IPU RXD(5) Receive Data CPn+3_4 Table 7 1 LVTTL I PD RXD(6) Receive Data CPn+3_5 Table 7 1 LVTTL I PU RXD(7) Receive Data (most significant bit) CPn+3_6 Table 7 1 LVTTL IPU RX_ER Receive Error Detected. Indicates that there has been an error received in the receive frame. TOTAL PINS 28 * n can be 0, 4, 8, or 12. † Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued) SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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