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C5C5EDELTA-RM/D 数据表(PDF) 82 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 82 Page - NXP Semiconductors |
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82 / 114 page  82 CHAPTER 3: ELECTRICAL SPECIFICATIONS C Clock Timing Specifications The system clock timing is shown in Figure 13 and described in Table 41. Figure 13 System Clock Timing Diagram Tsc Tsh SCLK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 SCLKX CCLKn TccN Tsl Tcch Tccl Table 41 System Clock Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tsc System Cycle Time 3.76 ns 266MHz core clock Tsh Sys Clk High Pulse 45 55 Duty cycle* * Pulse duty cycle measured at crossing voltage of SCLK/SCLKX Tsl Sys Clk Low Pulse 45 55 Duty cycle* Tcc0 CCLK0 Cycle Time 647.67 ns T1† Tcc1 CCLK1 Cycle Time 488.28 ns E1† Tcc2 CCLK2 Cycle Time 29.097 ns E3† Tcc3 CCLK3 Cycle Time 22.353 ns T3† Tcc4 CCLK4 Cycle Time 20.00 ns RMII† Tcc5 CCLK5 Cycle Time 9.412 ns Fibre Channel† Tcc6 CCLK6 Cycle Time 8.00 ns GMII† Tcc7 CCLK7 Cycle Time 6.43 ns OC-3† Tcch CCLKm High Time 40% 60% % cycle pulse is high Tccl CCLKm Low Time 40% 60% % cycle pulse is low Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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