| 数据搜索系统,热门电子元器件搜索 |
|
C5C5EDELTA-RM/D 数据表(PDF) 34 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
C5C5EDELTA-RM/D 数据表(HTML) 34 Page - NXP Semiconductors |
|
34 / 114 page ![]() 34 CHAPTER 2: SIGNAL DESCRIPTIONS C DS1/T1 Framer Interface Configuration Table 8 describes the serial framer interface signals. For each CP (0-15), you can implement one serial Framer interface. 10/100 Ethernet (RMII) Configuration Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface (RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface. Table 8 DS1/T1 Framer Interface Signals SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 Table 7 1 LVTTL O PD TCLK Transmit Clock (1.544MHz) CPn_1 Table 7 1 LVTTL I PU RCLK Receive Clock (1.544MHz) CPn_2 Table 7 1 LVTTL O PD TData Transmit Data CPn_3 Table 7 1 LVTTL O PU TFrame Transmit Frame Synchronization CPn_4 Table 7 1 LVTTL I PD RData Receive Data CPn_5 Table 7 1 LVTTL I PU RFrame Receive Frame Synchronization CPn_6 Table 7 1 nc ncPU nc nc TOTAL PINS 7 * n can be from 0 to 15. See Table 7. † Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. Table 9 10/100 Ethernet Signals SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 Table 7 1 LVTTL O PD REF_CLK Transmit and Receive Clock (50MHz) CPn_1 Table 7 1 LVTTL I PU CRS_DV Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle. CPn_2 Table 7 1 LVTTL O PD TXD(0) Transmit Data 0 (first on wire) CPn_3 Table 7 1 LVTTL O PU TXD(1) Transmit Data 1 (second on wire) CPn_4 Table 7 1 LVTTL I PD RXD(0) Receive Data 0 (first on wire) CPn_5 Table 7 1 LVTTL I PU RXD(1) Receive Data 1 (second on wire) CPn_6 Table 7 1 LVTTL OPU TX_EN Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. TOTAL PINS 7 * n can be from 0 to 15. See Table 7. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |