C5C5EDELTA-RMSLASHD datasheet(32/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

CP Interface Signals

The C-5e NP’s 16 CPs support various network physical interfaces, providing a serial

interface to the PHY layer. Interfaces are configured via bits in the C-5e NP register set.

Many interfaces are possible by programming the configuration registers. CPs can be

used individually or in a cluster (four CPs) to implement the various interfaces.

Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven

physical I/O pins associated with each CP. All pins are capable of receiving data, with some

configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can

be configured as differential pairs for LVPECL compatibility.

In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally

configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four

CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for

receive and four for transmit) or four CPs that share the transmit and receive functions for

non-wire speed applications.

During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial

Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the

SDPs, with each getting access to the necessary I/O pins.

The signals for the following CP physical interfaces are included in this section:

• DS1/T1 Framer Interface Configuration

• 10/100 Ethernet (RMII) Configuration

• Gigabit Ethernet (GMII) Configuration

• Gigabit Ethernet and Fibre Channel TBI Configuration

• SONET OC-3 Transceiver Interface Configuration

• SONET OC-12 Transceiver Interface Configuration

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D 数据表(PDF) 32 Page - NXP Semiconductors