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C5C5EDELTA-RM/D 数据表(PDF) 92 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 92 Page - NXP Semiconductors

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92
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in Figure 21 and described in Table 50.
Figure 21 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
Tslc
Tslss
Tslhd
Tslsd
Tslhs
SICL
SIDA
Tslst
Tslb
Table 50 Low Speed Serial Interface Timing Description
SYMBOL
PARAMETER
MIN
MAX
UNIT
Tslc
SICL Cycle Time
2500
ns
Tslss
Set-up Time for Repeated START Condition
600
ns
Tslhs
Hold Time START Condition
600
ns
Tslsd
Data Set-up Time
250
ns
Tslhd
Data Hold Time
0.0
ns
Tslst
Set-up Time for STOP Condition
600
ns
Tslb
Bus Free Time Between a STOP and START Condition
1250
ns
Cmax
Capacitive load for each line of the bus
400
pF
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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