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C5C5EDELTA-RM/D 数据表(PDF) 36 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 36 Page - NXP Semiconductors

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36
CHAPTER 2: SIGNAL DESCRIPTIONS
C
Figure 4 GMII/TBI Transmit and Receive Pin Configurations
Cluster
0
Cluster
1
Cluster
2
Cluster
3
Port 1
Port 2
Port 3
Port 4
}
}
}
}
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
Single Cluster Mode
Pin Configuration
Port 1
Port 2
}
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
Two Cluster Mode
Pin Configuration
nc
nc
nc
nc
}
nc = not connected
Cluster
0
Cluster
1
Cluster
2
Cluster
3
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME*
PIN #†
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
Table 7 1
LVTTL
O
PD
T_CLK
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
CPn_1
Table 7 1
LVTTL
I
PU
TCLKI
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
CPn_2
Table 7 1
LVTTL
O
PD
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CPn_3
Table 7 1
LVTTL
O
PU
TXD(1)
Transmit Data
CPn_4
Table 7 1
LVTTL
O
PD
TXD(2)
Transmit Data
CPn_5
Table 7 1
LVTTL
O
PU
TXD(3)
Transmit Data
CPn_6
Table 7 1
LVTTL
O
PU
TX_EN
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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