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C5C5EDELTA-RM/D 数据表(PDF) 87 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 87 Page - NXP Semiconductors

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AC Timing Specifications
87
03
OC-3 Timing Specifications
The OC-3 interface timing is shown in Figure 17 and described in Table 46.
Figure 17 OC-3 Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn_2
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn_3
CPn_0
CPn_1
CPn_4
CPn_5
Tc3t
Tc3r
Tc3d
Tc3i
Tc3s
Tc3h
Tc3s
Tc3h
Table 46 OC-3 Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tc3t
OC-3 Transmit Cycle Time
6.43
ns
Tc3i
OC-3 Pulse Width
2.0
ns
Tc3r
OC-3 Receive Cycle Time*
* 155.52MHz
6.0
ns
Tc3d
OC-3 Clock Duty Cycle
40
60
%
Tc3s
OC-3 Setup Time
2.0
ns
Tc3h
OC-3 Hold Time
0.0
ns
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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