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数据搜索系统，热门电子元器件搜索 |
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C5C5EDELTA-RM/D 数据表(PDF) 84 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 84 Page - NXP Semiconductors |
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84 / 114 page  84 CHAPTER 3: ELECTRICAL SPECIFICATIONS C 10/100 Ethernet Timing Specifications The 10/100 Ethernet interface timing is shown in Figure 15 and described in Table 43. Figure 15 10/100 Ethernet Timing Diagram Table 42 DS1/DS3 Ethernet Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tcdt DS1/DS3 Transmit Cycle Time 647/22.4 ns Tcdo DS1/DS3 Output Time 3.0/3.0 400/15.0 ns Tcdr DS1/DS3 Receive Cycle Time 647/22.4 ns Tcds DS1/DS3 Setup Time 2.0 ns Tcdh DS1/DS3 Hold Time 0 ns CPn_0 (TCLK) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 CPn_2/3/6 (Tx) CPn_1/4/5 (Rx) Tcet Tceo Tces Tceh Table 43 10/100 Ethernet Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tcet Transmit Cycle Time* * STD/Fast Ethernet 20 ns Tceo Output Time 3.0 15.0 ns Tces Setup Time 2.0 ns Tceh Hold Time 0 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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