C5C5EDELTA-RMSLASHD datasheet(98/114 Pages) NXP

部件名	C5C5EDELTA-RM/D

功能描述	C-5e NETWORK PROCESSOR SILICON REVISION A1

PDF	114 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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CHAPTER 3: ELECTRICAL SPECIFICATIONS

TLU Timing Specifications

The TLU timing specifications are shown in Figure 25 and described in Table 55.

Figure 25 TLU Timing Diagram

TCLKI

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

T_ctl

TAn

TDn

(output)

TDn

(input)

Ttc

Ttdo

Ttco

Ttao

Ttdv

Ttds

Ttdz

Ttdh

Table 55 TLU Timing Description

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Ttc

TLU Cycle Time

7.5

Ttco

TLU Ctrl Output

0.8

3.4

Ttao

TLU Addr Output

0.8

3.4

Ttds

TLU Data Setup

1.0

Ttdh

TLU Data Hold

1.2

Ttdo

TLU Data Output

0.8

3.7

Ttdz

TLU Data Clk to Tri*

* Not fully tested, values based on design/characterization.

0.8

3.7

Ttdv

TLU Data Clk to Driven*

0.8

3.7

Table 56 Signal Groups in TLU Timing Diagrams

SIGNAL GROUP

INCLUDED SIGNALS

Control (T_ctl)

TCE0X - TCE3X, TWE0X - TWE3X

Address (TAn)

TA0 - TA21

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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