C5C5EDELTA-RMSLASHD datasheet(49/114 Pages) NXP

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Pin Descriptions Grouped by Function

• Power X(CSIX-L0) Mode mappings are listed in Table 23

• CSIX-L1 Mode mappings are listed in Table 24

When configuring two C-5e network processors back-to-back using the Fabric Port, set

up the transmit side of each C-5e network processor in Utopia ATM mode and the receive

side of each C-5e network processor in Utopia PHY mode.

Table 20 Utopia1*, 2*, 3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5E NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

C-5E NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

FRXCTL0

Output

RxEnb*

Pullup or No

Connection

FTXCTL0

Output

TxEnb*

Pullup or No

Connection

FRXCTL1

Input

RxClav

FTXCTL1

Input

TxClav

FRXCTL2

Input

RxSOC

FTXCTL2

Output

TxSOC

FRXCTL3

Input

n/a

FTXCTL3

Input

n/a

FRXCTL4

Input

n/a

FTXCTL4

Input

n/a

FRXCTL5

Input

n/a

FTXCTL5

Input

n/a

FRXCTL6

Input

RxPrty

FTXCTL6

Output

TxPrty

* Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.

Table 21 Utopia1*, 2*, 3 PHY Mode, C-5e Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5E NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

C-5E NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

FRXCTL0

Input

TxEnb*

Pullup

FTXCTL0

Input

RxEnb*

Pullup

FRXCTL1

Output

TxClav

No Connection

FTXCTL1

Output

RxClav

No Connection

FRXCTL2

Input

TxSOC

FTXCTL2

Output

RxSOC

FRXCTL3

Input

n/a

FTXCTL3

Input

n/a

FRXCTL4

Input

n/a

FTXCTL4

Input

n/a

FRXCTL5

Input

n/a

FTXCTL5

Input

n/a

FRXCTL6

Input

TxPrty

FTXCTL6

Output

RxPrty

* Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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