C5C5EDELTA-RMSLASHD datasheet(96/114 Pages) NXP

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CHAPTER 3: ELECTRICAL SPECIFICATIONS

BMU Timing

Specifications

The BMU timing specifications are shown in Figure 24 and described in Table 53.

The BMU synchronous DRAM interface is PC100-compliant and designed to work with

industry standard SDRAM components with 12 or fewer address lines. The information

below is intended to provide the output, setup, and hold data required to design this

interface without duplicating the transaction waveform diagrams in SDRAM data sheets.

Figure 24 BMU Timing Diagram

MDCLK

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

M_ctl

MAn

MDn

(output)

MDn

(input)

Tmc

Tmdo

Tmco

Tmao

Tmdv

Tmds

Tmdz

Tmdh

Table 53 BMU Timing Description

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Tmc

BMU Cycle Time

7.5

Tmco

BMU Ctrl Output

0.8

3.4

Tmao

BMU Addr Output

0.8

3.4

Tmds

BMU Data Setup

0.5

Tmdh

BMU Data Hold

1.1

Tmdo

BMU Data Output

0.8

4.0

Tmdz

BMU Data Clk to Tri*

* Not fully tested, values based on design/characterization.

0.8

4.0

Tmdv

BMU Data Clk to Driven*

0.8

4.0

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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