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C5C5EDELTA-RM/D 数据表(PDF) 100 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 100 Page - NXP Semiconductors

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
C
Table 57 QMU SRAM (Internal Mode) Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tqc
QMU Cycle Time
5.7
ns
Tqco
QMU Ctrl Output
0.8
3.4
ns
Loading is 50
Ω
transmission line.
Tqao
QMU Addr Output
0.8
3.4
ns
Loading is 50
Ω
transmission line.
Tqds
QMU Data Setup
0.8
ns
Tqdh
QMU Data Hold
0.8
ns
Tqdo
QMU Data Output
0.9
3.4
ns
Loading is 50
Ω
transmission line.
Tqdz
QMU Data Clk to Tri*
* Not fully tested, values based on design/characterization.
0.9
3.4
ns
Tqdv
QMU Data Clk to
Driven*
0.9
3.4
ns
Table 58 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Control (Q_ctl)
QWEX
Address (QAn)
QA0-QA16
Data (QDn)
QD0-QD31, QDPL, QDPH
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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