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C5C5EDELTA-RM/D 数据表(PDF) 31 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 31 Page - NXP Semiconductors |
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31 / 114 page  Pin Descriptions Grouped by Function 31 03 Clock Signals Table 6 describes the C-5e NP clock signals. Table 6 Clock and Reference Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION SCLK* SCLKX* * SCLK and SCLKX must not be AC-coupled. G15 F15 1 1 LVPECL LVPECL I I Core Clock Rate (Differential) CCLK0 G14 1 LVTTL I PD 1_544MHZ_CLK (T1)† † The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one or more CCLKn inputs for other frequencies. Contact your Motorola representative for more information. CCLK1 F14 1 LVTTL I PD 2_048MHZ_CLK (E1)† CCLK2 E14 1 LVTTL I PD 34_368MHZ_CLK (E3)† CCLK3 G13 1 LVTTL I PD 44_736MHZ_CLK (T3)† CCLK4 F13 1 LVTTL I PD 50MHZ_CLK (100Mbit Ethernet)† CCLK5 E13 1 LVTTL I PD 106_25MHZ_CLK (Fibre Channel)† CCLK6 F12 1 LVTTL I PD 125MHZ_CLK (Gigabit Ethernet)† CCLK7 E12 1 LVTTL I PD 155_52MHZ_CLK (OC-3)† CPREF‡ ‡ If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in Table 38 on page 75. If none of the CPs are configured for LVPECL operation, then the CPREF pin can be left unconnected. G12 1 LVPECL I PD Reference TOTAL 11 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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