C5C5EDELTA-RMSLASHD datasheet(112/114 Pages) NXP

112 / 114 page

112

INDEX

Serial Interface 43

Serial Port 43

Test 58

TLU SRAM Interface 54

SONET OC-12 Transceiver Interface Configuration 40

SONET OC-3 Transceiver Interface Configuration 39

Specifications

10/100 Ethernet Timing 84

AC Timing 81

BMU Timing 96

Clock Timing 82

CP Timing 83

DS1/DS3 Timing 83

Electrical 73

Executive Processor Timing 89

Fabric Processor Timing 94

Gigabit GMII Ethernet, TBI and MII Interface Timing

Specification 85

Low Speed Serial Interface Timing 92

MDIO Serial Interface Timing 91

Mechanical 103

OC-12 Timing 88

OC-3 Timing 87

PCI Timing 89

PROM Interface Timing 93

QMU Timing 99

TLU Timing 98

XP Timing 89

System Clock Timing Description 82

System Clock Timing Diagram 82

System Interfaces

Executive Processor 23

Table Lookup Unit 25

Test Signals 58

Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test

Routines 58

Timing Outline

PROM Interface 46

TLU Signal Groups 98

TLU SRAM Interface Signals 54

TLU Timing Description 98

TLU Timing Diagram 98

TLU Timing Specifications 98

Transceiver Interface Configuration

SONET OC-12 40

SONET OC-3 39

Transmit and Receive Pin Combinations for Gigabit Ethernet and

FibreChannel 35

Utopia2/Utopia3 ATM Mode, C-5e Network Processor to Fabric

Interface Pin Mapping 49

Utopia2/Utopia3 PHY Mode, C-5e Network Processor to Fabric

Interface Pin Mapping 49

XP Timing Specifications 89

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D 数据表(PDF) 112 Page - NXP Semiconductors

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