CS5535 datasheet(313/555 Pages) NSC

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DIVIL Register Descriptions (Continued)

5.6.2.9

Local BAR - Flash Chip Select (DIVIL_LBAR_FLSH[x])

See Section 4.6.1 "LBARs and Comparators" on page 97

for operational details.

The NAND Flash control registers take 16 bytes of I/O

space. NOR Flash maps into some multiple of 4k bytes.

There are two forms of this LBAR depending on the space,

memory or I/O, Flash Device 0 is mapped into. Space is

determined by bit 34 of the LBAR.

Local BAR - Flash Chip Select 0 (DIVIL_LBAR_FLSH0)

Uses FLASH_CS0# and FLASH_CE0#.

Local BAR - Flash Chip Select 1 (DIVIL_LBAR_FLSH1)

Uses FLASH_CS1# and FLASH_CE1#.

Local BAR - Flash Chip Select 2 (DIVIL_LBAR_FLSH2)

Uses FLASH_CS2# and FLASH_CE2#.

Local BAR - Flash Chip Select 3 (DIVIL_LBAR_FLSH3)

Uses FLASH_CS3# and FLASH_CE3#.

47:44

IO_MASK

I/O Address Mask Value. See discussion in Section 4.6.1 "LBARs and Comparators"

on page 97

43:33

RSVD

Reserved. Reads return 0; writes have no effect.

LBAR_EN

LBAR Enable.

0: Disable LBAR.

1: Enable LBAR.

31:17

RSVD

Reserved. Reads return 0; writes have no effect.

RSVD

Reserved. Always write 0.

15:7

BASE_ADDR

Base Address in I/O Space. See discussion in Section 4.6.1 "LBARs and Compara-

tors" on page 97

6:0

RSVD

Reserved. Reads return 0; writes have no effect.

DIVIL_LBAR_PMS Bit Descriptions (Continued)

Bit

Name

Description

MSR Address

51400010h

Type

R/W

Reset Value

00000000_00000000h

MSR Address

51400011h

Type

R/W

Reset Value

00000000_00000000h

MSR Address

51400012h

Type

R/W

Reset Value

00000000_00000000h

MSR Address

51400013h

Type

R/W

Reset Value

00000000_00000000h

DIVIL_LBAR_FLSH[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

IO_MASK

MEM_MASK

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

BASE_ADDR

RSVD

BASE_ADDR

RSVD

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