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数据搜索系统，热门电子元器件搜索 |
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CS5535 数据表(PDF) 316 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 316 Page - National Semiconductor (TI) |
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316 / 555 page  www.national.com 316 Revision 0.8 DIVIL Register Descriptions (Continued) 5.6.2.11 Ball Options Control (DIVIL_BALL_OPTS) 24 LPC_DISABLE_ IO LPC Disable I/O. If high, discard all I/O writes which would otherwise go to the LPC by default. For reads, return all 1s. “Default” means any address not explicitly mapped into on-chip legacy I/O space or claimed by an LBAR hit. 23 RSVD Reserved. Reads return value written. Defaults to 0. 22:20 UART2_ENABLE [2:0] UART2 Enable. 0xx: UART1 not enabled into DIVIL I/O space; use LPC. 100: UART1 enabled into I/O base 02E8h (COM4). 101: UART1 enabled into I/O base 02F8h (COM3). 110: UART1 enabled into I/O base 03E8h (COM2). 111: UART1 enabled into I/O base 03F8h (COM1). If UART1 and UART2 are set to the same I/O base, a decode error is generated on access. 19 RSVD Reserved. Reads return value written. Defaults to 0 18:16 UART1_ENABLE [2:0] UART1 Enable. 0xx: UART1 not enabled into DIVIL I/O space; use LPC. 100: UART1 enabled into I/O base 02E8h (COM4). 101: UART1 enabled into I/O base 02F8h (COM3). 110: UART1 enabled into I/O base 03E8h (COM2). 111: UART1 enabled into I/O base 03F8h (COM1). If UART1 and UART2 are set to the same I/O base, a decode error is generated on access. 15:2 RSVD Reserved. Reads return value written. Defaults to 0 1 RTC_ENABLE1 Real-Time Clock Map 1. Routes I/O port locations 072h and 073h to the internal RTC high RAM or LPC. 0: RTC high RAM routed to LPC bus. 1: RTC high RAM routed to internal RTC. (Default) 0 RTC_ENABLE0 Real-Time Clock Map 0. Routes I/O port locations 070h and 071h internal RTC or LPC. Writes to port 070h (Index) are always routed internal. The MSB is used to estab- lish the NMI enable state. 0: RTC routed to LPC bus. 1: RTC routed to internal RTC. (Default) MSR Address 51400015h Type R/W Reset Value 00000x7xh DIVIL_BALL_OPTS Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87654321 0 RSVD DIVIL_LEG_IO Bit Description (Continued) Bit Name Description |
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