CS5535 datasheet(318/555 Pages) NSC

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Revision 0.8

DIVIL Register Descriptions (Continued)

5.6.2.12

Soft IRQ (DIVIL_SOFT_IRQ)

5.6.2.13 Soft Reset (DIVIL_SOFT_RESET)

5.6.2.14

Access Control DMA Request (DIVIL_AC_DMA)

The controls below only affect memory and I/O accesses to the target slaves. MSR accesses are not affected. However,

MSR writes during DMA may have unintended side effects.

Note that when in demand or block mode, the UART reads and writes are disallowed; no corresponding mechanism exists

to allow UART controller reads or writes during UART activity. If attempted, CPU writes have no effect and the CPU reads

return all 1s.

MSR Address

51400016h

Type

R/W

Reset Value

00000000h

DIVIL_SOFT_IRQ Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

DIVIL_SOFT_IRQ Bit Descriptions

Bit

Name

Description

31:1

RSVD

Reserved. Reads return 0. Writes have no effect.

SOFT_IRQ

Soft IRQ. This bit can be written high or low. and is connected to the soft IRQ input of

the IRQ Mapper. Hence, writing high causes an interrupt while writing low clears it.

Reads return the value written.

MSR Address

51400017h

Type

R/W

Reset Value

00000000h

DIVIL_SOFT_RESET Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

DIVIL_SOFT_RESET Bit Descriptions

Bit

Name

Description

31:1

RSVD

Reserved. Reads return 0. Writes have no effect.

SOFT_RESET

Soft Reset. A bit that when written to a 1 causes the system to hard reset. Reads

return 0.

MSR Address

5140001Eh

Type

R/W

Reset Value

00000000h

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