CS5535 datasheet(325/555 Pages) NSC

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PIT Register Descriptions (Continued)

5.8.2

PIT Native Registers

5.8.2.1

PIT Timer 0 Counter - System (PIT_TMR0_CNTR_SYS)

5.8.2.2

PIT Timer 0 Status - System (PIT_TMR0_STS_SYS)

PIT_CNTR_ACC_

DLY_EN

PIT Counter Access Delay Enable. Used as an access delay enable for the read and

write operations of the PIT counters. This bit introduces a 1 µs delay between succes-

sive reads and/or writes of the PIT counters. This bit is intended to ensure that older,

DOS-based programs that rely on the PIT timing access to be 1 µs still function prop-

erly.

0: Disable access delay.

1: Enable access delay.

3:2

RSVD

Reserved. Read zero. Write “don’t care”.

1PIT_CNTR1_EN

PIT Counter 1 Enable.

0: Sets GATE1 input low.

1: Sets GATE1 input high.

0PIT_CNTR0_EN

PIT Counter 0 Enable.

0: Sets GATE0 input low.

1: Sets GATE0 input high.

Note:

PIT_CNTR2_EN (PIT Counter 2 Enable) bit is located at I/O Address 61h[0] (see Section 5.8.2.8 "Port B Control

(PIT_PORTBCTL)" on page 330).

I/O Address

40h

Type

Reset Value

00h

PIT_TMR0_CNTR_SYS_ Register Map

CNTR0

PIT_TMR0_CNTR_SYS Bit Description

Bit

Name

Description

7:0

CNTR0

Counter 0 Value. Provides the base counter value.

I/O Address

40h

Type

Reset Value

00h

PIT_TMR0_STS_SYS Register Map

I/O Address 43h[7:0] = 1101xx10 or 0010xxxx

CNTR0_CUR_COUNT

I/O Address 43h[7:0] = 11110xx10

CNTR0_OUT

CNTR0_LOAD

CNTR0_RW

CNTR0_MODE

BCD

PIT_CNTRL Bit Descriptions (Continued)

Bit

Name

Description

CS5535 数据表(PDF) 325 Page - National Semiconductor (TI)

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