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数据搜索系统，热门电子元器件搜索 |
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CS5535 数据表(PDF) 324 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 324 Page - National Semiconductor (TI) |
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324 / 555 page  www.national.com 324 Revision 0.8 PIT Register Descriptions (Continued) 5.8.1 PIT Specific MSRs 5.8.1.1 PIT Shadow (PIT_SHDW) 5.8.1.2 PIT Count Enable (PIT_CNTRL) MSR Address 51400036h Type RO Reset Value 00h PIT_SHDW Register Map 76 54 32 10 PIT_SHDW PIT_SHDW Bit Descriptions Bit Name Description 7:0 PIT_SHDW (RO) PIT Shadow (Read Only). This 8-bit port sequences through the following list of shad- owed Programmable Interval Timer registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write to this regis- ter resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to that location. The read sequence for this register is: 1. Counter 0 LSB (least significant byte) 2. Counter 0 MSB 3. Counter 1 LSB 4. Counter 1 MSB 5. Counter 2 LSB 6. Counter 2 MSB 7. Counter 0 Command Word 8. Counter 1 Command Word 9. Counter 2 Command Word Note: The LSB / MSB of the count is the Counter base value, not the current value. In the case of counter mode 3, the LSB of the count is the Counter base value - 1 (even count value). Bits [7:6] of the command words are not used. MSR Address 51400037h Type R/W Reset Value 03h PIT_CNTRL Register Map 76 54 32 10 RSVD PIT_CNTR_ ACC_DLY_EN RSVD PIT_CNTR1_ EN PIT_CNTR0_ EN PIT_CNTRL Bit Descriptions Bit Name Description 7:5 RSVD Reserved. Read zero. Write “don’t care”. |
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