TMP86FS49AIUG datasheet(56/296 Pages) TOSHIBA

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3. Interrupt Control Circuit

3.3 Interrupt Sequence

TMP86FS49AIUG

A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the

level of current servicing interrupt is requested.

In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,

acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,

before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length

between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply

nested.

3.3.2

Saving/restoring general-purpose registers

During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,

includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are

saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using

the same data memory area for saving registers. The following methods are used to save/restore the general-

purpose registers.

3.3.2.1

Using PUSH and POP instructions

If only a specific register is saved or interrupts of the same source are nested, general-purpose registers

can be saved/restored using the PUSH/POP instructions.

Figure 3-3 Save/restore register using PUSH and POP instructions

3.3.2.2

Using data transfer instructions

To save only a specific register without nested interrupts, data transfer instructions are available.

Example :Save/restore register using PUSH and POP instructions

PINTxx:

PUSH

; Save WA register

(interrupt processing)

POP

; Restore WA register

RETI

; RETURN

PCL

PCH

PSW

At acceptance of

an interrupt

At execution of

PUSH instruction

At execution of

RETI instruction

At execution of

POP instruction

b-4

b-3

b-2

b-1

PCL

PCH

PSW

PCL

PCH

PSW

Address

(Example)

b-5

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