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TMP86FS49AIUG 数据表(PDF) 68 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 68 Page - Toshiba Semiconductor |
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68 / 296 page ![]() Page 52 5. I/O Ports 5.2 Port P1 (P17 to P10) TMP86FS49AIUG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P1 is also used as a timer/counter input/output, an external interrupt input and a divider output. Input/output mode is specified by the P1 control register (P1CR). During reset, the P1CR is initialized to "0" and port P1 becomes an input mode. And the P1DR is initialized to "0". When used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of P1CR should be set to "0". When used as an output port, the corresponding bit of P1CR should be set to "1". When used as a timer/counter output and a divider output, P1DR is set to "1" beforehand and the corresponding bit of P1CR should be set to "1". When P1CR is "1", the content of the corresponding output latch is read by reading P1DR. Note: Asterisk (*) indicates “1” or “0” either of which can be selected. Note: i = 7 to 0 Figure 5-3 Port 1 and P1CR Note: The port set to an input mode reads the terminal input data. Therefore, when the input and output modes are used together, the content of the output latch which is specified as input mode might be changed by executing a bit Manipulation instruction. Table 5-2 Register Programming for Multi-function Ports Function Programmed Value P1DR P1CR Port input, timer/counter input or external interrupt input *“0” Port “0” output “0” “1” Port “1” output, a timer output or a divider output “1” “1” P1i DQ DQ STOP OUTEN P1CRi P1CRi input Data input (P1DR) Data output (P1DR) Control output Control input Output latch |
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