TMP86FS49AIUG datasheet(81/296 Pages) TOSHIBA

81 / 296 page

Page 65

TMP86FS49AIUG

6. Watchdog Timer (WDT)

The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu-

rious noises or the deadlock conditions, and return the CPU to a system recovery routine.

The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter-

rupt request”. Upon the reset release, this signal is initialized to “reset request”.

When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter-

rupt.

Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to

effect of disturbing noise.

6.1

Watchdog Timer Configuration

Figure 6-1 Watchdog Timer Configuration

0034H

Overflow

WDT output

Internal reset

Binary counters

WDTOUT

Writing

clear code

Writing

disable code

WDTEN

WDTT

0035H

Watchdog timer control registers

WDTCR1

WDTCR2

INTWDT

interrupt

request

Interrupt request

Reset

request

Reset release

Clock

Clear

Controller

fc/223 or fs/215

fc/221 or fs/213

fc/219 or fs/211

fc/217 or fs/29

TMP86FS49AIUG 数据表(PDF) 81 Page - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 81 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载