TMP86FS49AIUG datasheet(28/296 Pages) TOSHIBA

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Page 12

2. Operational Description

2.2 System Clock Controller

TMP86FS49AIUG

2.2.2

Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware

from the basic clock (fc or fs). The timing generator provides the following functions.

1. Generation of main system clock

2. Generation of divider output (DVO) pulses

3. Generation of source clocks for time base timer

4. Generation of source clocks for watchdog timer

5. Generation of internal source clocks for timer/counters

6. Generation of warm-up clocks for releasing STOP mode

2.2.2.1

Configuration of timing generator

The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,

and machine cycle counters.

An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and

TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler

and the divider are cleared to “0”.

Figure 2-4 Configuration of Timing Generator

Multi-

plexer

High-frequency

clock fc

Low-frequency

clock fs

Divider

SYSCK

fc/4

fc or fs

Machine cycle counters

Main system clock generator

DV7CK

Multiplexer

Warm-up

controller

Watchdog

timer

A0 Y0

A1 Y1

17 18 19 20 21

Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

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