TMP86FS49AIUG datasheet(85/296 Pages) TOSHIBA

部件名	TMP86FS49AIUG

功能描述	8 Bit Microcontroller

PDF	296 Pages

Scroll/Zoom	100%

制造商	TOSHIBA [Toshiba Semiconductor]

网页	http://www.semicon.toshiba.co.jp/eng

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Page 69

TMP86FS49AIUG

6.2.5

Watchdog Timer Reset

When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset

request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset

time is maximum 24/fc [s] (1.5

µs @ fc = 16.0 MHz).

Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-

quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-

cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate

value because it has slight errors.

Figure 6-2 Watchdog Timer Interrupt

Clock

Binary counter

Overflow

INTWDT interrupt request

(WDTCR1<WDTOUT>= "0")

217/fc

219/fc [s]

(WDTT=11)

Write 4EH to WDTCR2

Internal reset

(WDTCR1<WDTOUT>= "1")

A reset occurs

TMP86FS49AIUG 数据表(PDF) 85 Page - Toshiba Semiconductor