TMP86FS49AIUG datasheet(74/296 Pages) TOSHIBA

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Page 58

5. I/O Ports

5.6 Port P5 (P54 to P50) (Large Current Port)

TMP86FS49AIUG

5.6

Port P5 (P54 to P50) (Large Current Port)

Port P5 is an 5-bit input/output port.

Port P5 is also used as an I2C Bus input/output.

When used as an input port and I2C Bus input/output, the corresponding output latch (P5DR) should be set to "1".

During reset, the P5DR is initialized to "1".

P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address.

When read the output latch data, the P5DR should be read. When read the terminal input data, the P5PRD register

should be read.

If a read instruction is executed for port P5, read data of bit 7 to 5 are unstable.

Note: i = 4 to 0

Figure 5-7 Port 5

P5DR

(0005H)

R/W

543

P54P53

P52P51

SDA

P50

SCL

(Initial value: ***1 1111)

P5PRD

(000FH)

Read only

P54P53

P52P51

P50

Data output (P5DR)

Control output

STOP

OUTEN

P5i

Data input (P5PRD)

Output latch read (P5DR)

Control input

Output latch

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