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TMP86FS49AIUG 数据表(PDF) 32 Page - Toshiba Semiconductor

部件名 TMP86FS49AIUG
功能描述  8 Bit Microcontroller
PDF  296 Pages
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制造商  TOSHIBA [Toshiba Semiconductor]
网页  http://www.semicon.toshiba.co.jp/eng
标志 TOSHIBA - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 32 Page - Toshiba Semiconductor

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Page 16
2. Operational Description
2.2 System Clock Controller
TMP86FS49AIUG
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1
Operating Mode and Conditions
Operating Mode
Oscillator
CPU Core
TBT
Other
Peripherals
Machine Cycle
Time
High
Frequency
Low
Frequency
Single clock
RESET
Oscillation
Stop
Reset
Reset
Reset
4/fc [s]
NORMAL1
Operate
Operate
Operate
IDLE1
Halt
IDLE0
Halt
STOP
Stop
Halt
–
Dual clock
NORMAL2
Oscillation
Oscillation
Operate with
high frequency
Operate
Operate
4/fc [s]
IDLE2
Halt
SLOW2
Operate with
low frequency
4/fs [s]
SLEEP2
Halt
SLOW1
Stop
Operate with
low frequency
SLEEP1
Halt
SLEEP0
Halt
STOP
Stop
Halt
–
Note 2
SYSCR2<XEN> = "1"
STOP pin input
STOP pin input
STOP pin input
Interrupt
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<SYSCK> = "1"
SYSCR2<XTEN> = "0"
SYSCR2<SYSCK> = "0"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
Interrupt
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
Interrupt
SYSCR2<TGHALT> = "1"
Reset release
NORMAL1
mode
IDLE0
mode
(a) Single-clock mode
IDLE1
mode
NORMAL2
mode
IDLE2
mode
SYSCR2<XTEN> = "1"
SLOW2
mode
SLEEP2
mode
SLOW1
mode
SLEEP1
mode
SLEEP0
mode
RESET
(b) Dual-clock mode
STOP
SYSCR2<TGHALT> = "1"
Note 2



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