TMP86FS49AIUG datasheet(29/296 Pages) TOSHIBA

29 / 296 page

Page 13

TMP86FS49AIUG

Note 1: In single clock mode, do not set DV7CK to “1”.

Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care

Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.

Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after

release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.

2.2.2.2

Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different

types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one

machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A

machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

Figure 2-5 Machine Cycle

2.2.3

Operation Mode Control Circuit

The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-

frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,

dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and

SYSCR2). Figure 2-6 shows the operating mode transition diagram.

2.2.3.1

Single-clock mode

Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)

pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In

the single-clock mode, the machine cycle time is 4/fc [s].

(1)

NORMAL1 mode

In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.

The TMP86FS49AIUG is placed in this mode after reset.

Timing Generator Control Register

TBTCR

(0036H)

(DVOEN)

(DVOCK)

DV7CK

(TBTEN)

(TBTCK)

(Initial value: 0000 0000)

DV7CK

Selection of input to the 7th stage

of the divider

0: fc/28 [Hz]

1: fs

R/W

Main system clock

State

Machine cycle

1/fc or 1/fs [s]

TMP86FS49AIUG 数据表(PDF) 29 Page - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 29 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载