TMP86FS49AIUG datasheet(30/296 Pages) TOSHIBA

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Page 14

2. Operational Description

2.2 System Clock Controller

TMP86FS49AIUG

(2)

IDLE1 mode

In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are

halted; however on-chip peripherals remain active (Operate using the high-frequency clock).

IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1

mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF

(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance

of the interrupt, and the operation will return to normal after the interrupt service is completed. When

the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the

IDLE1 mode start instruction.

(3)

IDLE0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.

This mode is enabled by SYSCR2<TGHALT> = "1".

When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the

peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected

with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back

again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =

“1”, EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-

cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT

interrupt latch is set after returning to NORMAL1 mode.

2.2.3.2

Dual-clock mode

Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and

P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the

high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in

SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and

4/fs [s] (122

µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.

The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the low-

frequency oscillator should be turned on at the start of a program.

(1)

NORMAL2 mode

In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate

using the high-frequency clock and/or low-frequency clock.

(2)

SLOW2 mode

In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency

clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hard-

ware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes

into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1

mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.

(3)

SLOW1 mode

This mode can be used to reduce power-consumption by turning off oscillation of the high-fre-

quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

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