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TMP86FS49AIUG 数据表(PDF) 96 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 96 Page - Toshiba Semiconductor |
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96 / 296 page ![]() Page 80 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AIUG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR<ACAP1> to “1” captures the up-counter value into the timer reg- ister 1B (TC1DRB) with the auto-capture function. Use the auto-capture function in the operative condition of TC1. A cap- tured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Note: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Table 8-1 Internal Source Clock for TimerCounter 1 (Example: fc = 16 MHz, fs = 32.768 kHz) TC1CK NORMAL1/2, IDLE1/2 mode SLOW, SLEEP mode DV7CK = 0 DV7CK = 1 Resolution [ µs] Maximum Time Setting [s] Resolution [ µs] Maximum Time Setting [s] Resolution [ µs] Maximum Time Set- ting [s] 00 128 8.39 244.14 16.0 244.14 16.0 01 8.0 0.524 8.0 0.524 – – 10 0.5 32.77 m 0.5 32.77 m – – Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR<DV7CK> = “0”) LDW (TC1DRA), 1E84H ; Sets the timer register (1 s ÷ 211/fc = 1E84H) DI ; IMF = “0” SET (EIRL). 5 ; Enables INTTC1 EI ; IMF = “1” LD (TC1CR), 00000000B ; Selects the source clock and mode LD (TC1CR), 00010000B ; Starts TC1 Example 2 :Auto-capture LD (TC1CR), 01010000B ; ACAP1 ← 1 : : LD WA, (TC1DRB) ; Reads the capture value |
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