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TMP86FS49AIUG 数据表(PDF) 101 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 101 Page - Toshiba Semiconductor |
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101 / 296 page  Page 85 TMP86FS49AIUG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with TC1CR<TC1CK>. Figure 8-5 Window Mode Timing Chart Match detect TC1DRA INTTC1 interrput request interrput request Internal clock Counter TC1DRA TC1 pin input Internal clock Counter TC1 pin input INTTC1 (a) Positive logic (TC1S = 10) (b) Negative logic (TC1S = 11) ? ? Match detect 1 0 7 47 5 46 31 2 1 0 7 5 3 6 2 0 2 3 Counter clear Timer start 89 0 1 9 Timer start Counter clear Count start Count stop Count start Count start Count stop Count start |
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