TMP86FS49AIUG datasheet(106/296 Pages) TOSHIBA

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Page 90

8. 16-Bit TimerCounter 1 (TC1)

8.3 Function

TMP86FS49AIUG

Figure 8-7 PPG Output

Example :Generating a pulse which is high-going for 800 µs and low-going for 200

µs

(fc = 16 MHz)

Setting port

(TC1CR), 10000111B

; Sets the PPG mode, selects the source clock

LDW

(TC1DRA), 007DH

; Sets the cycle (1 ms

÷ 27/fc ms = 007DH)

LDW

(TC1DRB), 0019H

; Sets the low-level pulse width (200

µs ÷ 27/fc = 0019H)

(TC1CR), 10010111B

; Starts the timer

Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG

(fc = 16 MHz)

Setting port

(TC1CR), 10000111B

; Sets the PPG mode, selects the source clock

LDW

(TC1DRA), 007DH

; Sets the cycle (1 ms

÷ 27/fc µs = 007DH)

LDW

(TC1DRB), 0019H

; Sets the low-level pulse width (200

µs ÷ 27/fc = 0019H)

(TC1CR), 10010111B

; Starts the timer

(TC1CR), 10000111B

; Stops the timer

(TC1CR), 10000100B

; Sets the timer mode

(TC1CR), 00000111B

; Sets the PPG mode, TFF1 = 0

(TC1CR), 00010111B

; Starts the timer

PPG pin

Function output

Port output

enable

I/O port output latch

shared with PPG output

Data output

Toggle

Set

Clear

TC1CR<TFF1>

Write to TC1CR

Internal reset

Match to TC1DRB

Match to TC1DRA

TC1CR<TC1S> clear

Timer F/F1

INTTC1 interrupt request

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