TMP86FS49AIUG datasheet(111/296 Pages) TOSHIBA

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TMP86FS49AIUG

9.3

Function

The timer/counter 2 has three operating modes: timer, event counter and window modes.

And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to

NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable.

9.3.1

Timer mode

In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the con-

tents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is

cleared. Counting up is resumed after the counter is cleared.

When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a

interrupt by matching upper 5-bits only. Though, in this situation, it is necessary to set TC2DRH only.

Note:When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW1 mode

to NORMAL2 mode.

Table 9-1

Source Clock (Internal clock) for Timer/Counter2 (at fc = 16 MHz, DV7CK=0)

TC2C

NORMAL1/2, IDLE1/2 mode

SLOW1/2 mode

SLEEP1/2 mode

DV7CK = 0

DV7CK = 1

Resolution

Maximum Time Set-

ting

Resolution

Maximum Time Set-

ting

Resolu-

tion

Maxi-

mum

Time

Setting

Resolu-

tion

Maxi-

mum

Time

Setting

000

524.29 [ms]

9.54 [h]

1 [s]

18.2 [h]

1 [s]

18.2 [h]

1 [s]

18.2 [h]

001

512.0 [ms]

33.55 [s]

0.98 [ms]

1.07 [min]

0.98 [ms]

1.07

[min]

0.98 [ms]

1.07

[min]

010

16.0 [ms]

1.05 [s]

16.0 [ms]

1.05 [s]

–

011

0.5 [ms]

32.77 [ms]

0.5 [ms]

32.77 [ms]

–

100

–

62.5 [ns]

–

101

30.52 [ms]

2 [s]

30.52 [ms]

2 [s]

–

Example :Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz )

LDW

(TC2DR), 061AH

; Sets TC2DR (25 ms

÷ 28/fc = 061AH)

; IMF= “0”

SET

(EIRE). 6

; Enables INTTC2 interrupt

; IMF= “1”

(TC2CR), 00001000B

; Source clock / mode select

(TC2CR), 00101000B

; Starts Timer

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