 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TMP86FS49AIUG 数据表(PDF) 143 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP86FS49AIUG 数据表(HTML) 143 Page - Toshiba Semiconductor |
|
|
143 / 296 page  Page 127 TMP86FS49AIUG Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the TCjCR<TFFj> setting upon stopping of the timer. Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PDOj pin to the high level. Note 3: j = 5, 6 Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port LD (TTREG6), 3DH : 1/1024 ÷27/fc÷2 = 3DH LD (TC6CR), 00010001B : Sets the operating clock to fc/27, and 8-bit PDO mode. LD (TC6CR), 00011001B : Starts TC6. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
