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ST10F167 数据表(PDF) 65 Page - STMicroelectronics |
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ST10F167 数据表(HTML) 65 Page - STMicroelectronics |
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65 / 69 page ![]() 65/69 ST10F167 20.5.10 External Bus Arbitration VDD =5 V ± 5%, VSS =0 V, TA = -40 to +85 °C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF Table 20.9 External Bus Arbitration Characteristics Parameter Symbol Max. CPU Clock =20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t61 SR 35 – 35 – ns CLKOUT to HLDA high or BREQ low delay t 62 CC – 20 – 20 ns CLKOUT to HLDA low or BREQ high delay t 63 CC – 20 – 20 ns CSx release t 64 CC – 20 – 20 ns CSx drive t 65 CC -5 25 -5 25 ns Other signals release t 66 CC – 20 – 20 ns Other signals drive t 67 CC -5 25 -5 25 ns |
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