ST10F167 datasheet(24/69 Pages) STMICROELECTRONICS

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ST10F167

CAPTURE/COMPARE (CAPCOM) UNITS

The CAPCOM units support generation and con-

trol of timing sequences on up to 32 channels. It

has a maximum resolution of 400 ns at 20MHz

system clock. The CAPCOM units are typically

used to handle high speed I/O tasks such as pulse

and waveform generation, pulse width modulation

(PMW), Digital to Analog (D/A) conversion, soft-

ware timing, or time recording relative to external

events.

Four 16-bit timers (T0/T1, T7/T8) with reload reg-

isters, provide two independent time bases for the

capture/compare register array.

The input clock for the timers is programmable to

several pre-scaled values of the internal system

clock, or may be derived from an overflow/under-

flow of timer T6 in module GPT2. This provides a

wide range of variation for the timer period and

resolution and allows precise adjustments to the

application specific requirements. In addition, ex-

ternal count inputs for CAPCOM timers T0 and T7

allow event scheduling for the capture/compare

registers relative to external events.

Both of the two capture/compare register arrays

contain 16 dual purpose capture/compare regis-

ters, each of which may be individually allocated to

either CAPCOM timer T0 or T1 (T7 or T8, respec-

tively), and programmed for capture or compare

function. Each register has one port pin associated

with it which serves as an input pin for triggering

the capture function, or as an output pin (except

for CC24...CC27) to indicate the occurrence of a

compare event.

When a capture/compare register has been se-

lected for capture mode, the current contents of

the allocated timer will be latched (‘captured) into

the capture/compare register in response to an ex-

ternal event at the port pin which is associated with

this register. In addition, a specific interrupt re-

quest for this capture/compare register is generat-

ed. Either a positive, a negative, or both a positive

and a negative external signal transition at the pin

can be selected as the triggering event. The con-

tents of all registers which have been selected for

one of the five compare modes are continuously

compared with the contents of the allocated tim-

ers. When a match occurs between the timer value

and the value in a capture/compare register, spe-

cific actions will be taken, based on the selected

compare mode.

Table 9.1

Compare Mode Function

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Two registers operate on one pin; pin toggles on each compare match;

several compare events per timer period are possible.

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