ST10F167 datasheet(22/69 Pages) STMICROELECTRONICS

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ST10F167

Note: Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-

Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respec-

tive XPnIR bit.

The ST10F167 provides an excellent mechanism

to identify and to process exceptions or error con-

ditions that arise during run-time, ‘Hardware

Traps’. Hardware traps cause an immediate non-

maskable system reaction which is similar to a

standard interrupt service (branching to a dedicat-

ed vector table location). The occurrence of a

hardware trap is additionally signified by an indi-

vidual bit in the trap flag register (TFR). Except

when another higher prioritized trap service is in

progress, a hardware trap will interrupt any actual

program execution. In turn, hardware trap services

can normally not be interrupted by standard or

PEC interrupts

Table 8.2 shows all of the possible exceptions or

error conditions that can arise during run-time.

GPT1 Timer 2

T2IR

T2IE

T2INT

00’0088h

22h

GPT1 Timer 3

T3IR

T3IE

T3INT

00’008Ch

23h

GPT1 Timer 4

T4IR

T4IE

T4INT

00’0090h

24h

GPT2 Timer 5

T5IR

T5IE

T5INT

00’0094h

25h

GPT2 Timer 6

T6IR

T6IE

T6INT

00’0098h

26h

GPT2 CAPREL Register

CRIR

CRIE

CRINT

00’009Ch

27h

A/D Conversion Complete

ADCIR

ADCIE

ADCINT

00’00A0h

28h

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00’00A4h

29h

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00’00A8h

2Ah

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00’011Ch

47h

ASC0 Receive

S0RIR

S0RIE

S0RINT

00’00ACh

2Bh

ASC0 Error

S0EIR

S0EIE

S0EINT

00’00B0h

2Ch

SSC Transmit

SCTIR

SCTIE

SCTINT

00’00B4h

2Dh

SSC Receive

SCRIR

SCRIE

SCRINT

00’00B8h

2Eh

SSC Error

SCEIR

SCEIE

SCEINT

00’00BCh

2Fh

PWM Channel 0...3

PWMIR

PWMIE

PWMINT

00’00FCh

3Fh

CAN Interface

XP0IR

XP0IE

XP0INT

00’0100h

40h

X-Peripheral Node

XP1IR

XP1IE

XP1INT

00’0104h

41h

X-Peripheral Node

XP2IR

XP2IE

XP2INT

00’0108h

42h

PLL Unlock

XP3IR

XP3IE

XP3INT

00’010Ch

43h

Table 8.1

Interrupt Sources, Flags, Vector and Trap Numbers (cont’d)

Source of Interrupt or

PEC Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

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