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ST10F167 数据表(PDF) 58 Page - STMicroelectronics |
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ST10F167 数据表(HTML) 58 Page - STMicroelectronics |
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58 / 69 page ![]() 58/69 ST10F167 CS hold after RD, WR t 41 CC 10 + t F – TCL - 15 + t F –ns ALE falling edge to RdCS, WrCS (with RW-delay) t 42 CC 20 + t A – TCL - 5 + t A –ns ALE falling edge to RdCS, WrCS (no RW-delay) t 43 CC -5 + t A –-5 + t A –ns RdCS to Valid Data In (with RW-delay) t 46 SR – 15 + t C – 2TCL - 35 + t C ns RdCS to Valid Data In (no RW-delay) t 47 SR – 50 + t C – 3TCL - 25 + t C ns RdCS, WrCS Low Time (with RW-delay) t 48 CC 40 + t C – 2TCL - 10 + t C –ns RdCS, WrCS Low Time (no RW-delay) t 49 CC 65 + t C – 3TCL - 10 + t C –ns Data valid to WrCS t 50 CC 35 + t C – 2TCL - 15 + t C –ns Data hold after RdCS t 51 SR 0 – 0 – ns Data float after RdCS (with RW-delay) t 53 SR – 30 + t F – 2TCL - 20 + tF ns Data float after RdCS (no RW-delay) t 68 SR – 5 + t F – TCL - 20 + t F ns Address hold after RdCS, WrCS t 55 CC -10 + t F – -10 + t F –ns Data hold after WrCS t 57 CC 10 + t F – TCL - 15 + t F –ns Table 20.7 Demultiplexed Bus Characteristics (cont’d) Parameter Symbol Max. CPU Clock =20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. 3 |
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