ST10F167 datasheet(20/69 Pages) STMICROELECTRONICS

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ST10F167

An efficient instruction set allows maximum use of

the CPU. The instruction set is classified into the

following groups:

•

Arithmetic Instructions

•

Logical Instructions

•

Boolean Bit Manipulation Instructions

•

Compare and Loop Control Instructions

•

Shift and Rotate Instructions

•

Prioritize Instruction

•

Data Movement Instructions

•

System Stack Instructions

•

Jump and Call Instructions

•

Return Instructions

•

System Control Instructions

•

Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes.

Possible operand types are bits, bytes and words.

A variety of direct, indirect or immediate address-

ing modes exist.

INTERRUPT SYSTEM

With an interrupt response time from 250ns to

600ns (in the case of internal program execution),

the ST10F167 reacts quickly to the occurrence of

non-deterministic events

The architecture of the ST10F167 supports sever-

al mechanisms for fast and flexible response to

service requests that can be generated from vari-

ous sources internal or external to the microcon-

troller. Any of these interrupt requests can be pro-

grammed to being serviced by the Interrupt Con-

troller or by the Peripheral Event Controller (PEC).

In a standard interrupt service, program execution

is suspended and a branch to the interrupt vector

table is performed. For a PEC service, just one cy-

cle is ‘stolen’ from the current CPU activity. A PEC

service is a single byte or word data transfer be-

tween any two memory locations with an addition-

al increment of either the PEC source or the desti-

nation pointer. An individual PEC transfer counter

is decremented for each PEC service, except for

the continuous transfer mode. When this counter

reaches zero, a standard interrupt is performed to

the corresponding source related vector location.

PEC services are suited to, for example, the trans-

mission or reception of blocks of data. The

ST10F167 has 8 PEC channels, each of which of-

fers fast interrupt-driven data transfer capabilities.

A separate control register which contains an in-

terrupt request flag, an interrupt enable flag and

an interrupt priority bitfield, exists for each of the

possible interrupt sources. Via its related register,

each source can be programmed to one of sixteen

interrupt priority levels. Once having been accept-

ed by the CPU, an interrupt service can only be in-

terrupted by a higher prioritized service request.

For the standard interrupt processing, each of the

possible interrupt sources has a dedicated vector

location.

Fast external interrupt inputs are provided to serv-

ice external interrupts with high precision require-

ments. These fast interrupt inputs, feature pro-

grammable edge detection (rising edge, falling

edge or both edges).

Software interrupts are supported by means of the

‘TRAP’ instruction in combination with an individu-

al trap (interrupt) number.

Table 8.1 shows all of the possible ST10F167 in-

terrupt sources and the corresponding hardware-

related interrupt flags, vectors, vector locations

and trap (interrupt) numbers

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