ST10F167 datasheet(48/69 Pages) STMICROELECTRONICS

48 / 69 page

48/69

ST10F167

20.5.2 Definition of Internal Timing

The internal operation of the ST10F167 is control-

led by the internal CPU clock fCPU. Both edges of

the CPU clock can trigger internal (e.g. pipeline) or

external (e.g. bus cycles) operations.

The specification of the external timing (AC Char-

acteristics) therefore depends on the time be-

tween two consecutive edges of the CPU clock,

called “TCL” (see Figure 20.4).

The CPU clock signal can be generated via differ-

ent mechanisms. The duration of TCLs and their

variation (and also the derived external timing) de-

pends on the mechanism used to generate fCPU.

This influence must be taken into consideration

when calculating the timings for the ST10F167.

Figure 20.4

Generation Mechanisms for the CPU Clock

20.5.3 Direct Drive

When pin P0.15 (P0H.7) is low (‘0’) during reset

the on-chip phase locked loop is disabled and the

CPU clock is directly driven from the oscillator with

the input clock signal.

The frequency of fCPU directly follows the frequen-

cy of fXTAL so the high and low time of fCPU (i.e. the

duration of an individual TCL) is defined by the

duty cycle of the input clock fXTAL.

The timings listed below that refer to TCLs there-

fore must be calculated using the minimum TCL

that is possible under the respective circumstanc-

es. This minimum value can be calculated via the

following formula:

For two consecutive TCLs the deviation caused by

the duty cycle of fXTAL is compensated so the du-

ration of 2TCL is always 1/fXTAL. The minimum

value TCLmin therefore has to be used only once

for timings that require an odd number of TCLs

(1,3,...). Timings that require an even number of

TCLs (2,4,...) may use the formula:

2TCL = 1/f

XTAL.

Note:The address float timings in Multiplexed bus mode

(t11 and t45) use the maximum duration of TCL

(TCLmax = 1/fXTAL *DCmax) instead of TCLmin.

TCL TCL

fCPU

fXTAL

fCPU

fXTAL

Phase Locked Loop Operation

Direct Clock Drive

TCL

min

1 f

⁄

XTAL*DCmin

duty cycle

ST10F167 数据表(PDF) 48 Page - STMicroelectronics

ST10F167 数据表(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载