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ST10F167 数据表(PDF) 12 Page - STMicroelectronics |
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ST10F167 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 69 page ![]() 12/69 ST10F167 3 FUNCTIONAL DESCRIPTION The architecture of the ST10F167 combines the advantages of both RISC and CISC processors and an advanced peripheral subsystem. The fol- lowing block diagram gives an overview of the dif- ferent on-chip components and of the advanced, high bandwidth internal bus structure of the ST10F167. Figure 3.1 Block Diagram Internal FLASH Memory CPU-Core Internal RAM 32 16 16 16 16 16 16 16 16 8 8 8 8 16 15 Interrupt Controller CAN Module XRAM Ext. Bus Con- troller 10-Bit ADC Port 6 Port 5 Port 3 Port 7 Port 8 ASC (USART) SSC PWM CAPCOM 2 CAPCOM 1 GPT1 GPT2 BRG BRG Watchdog OSC. PEC T2 T3 T4 T5 T6 T7 T8 T0 T1 ... ... ... VR02060C 3 |
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