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ST10F167 数据表(PDF) 40 Page - STMicroelectronics |
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ST10F167 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 69 page ![]() 40/69 ST10F167 Notes 1:The system configuration is selected during reset. 2:Bit WDTR indicates a watchdog timer triggered reset. 3:The Interrupt Control Registers XPnIC, control interrupt requests from integrated X-Bus periph- erals. Nodes, where no X-Peripherals are connected, may be used to generate software con- trolled interrupt requests by setting the respective XPnIR bit. WDT FEAEh 57h Watchdog Timer Register (read only) 0000h WDTCON FFAEh D7h Watchdog Timer Control Register 000Xh2) XP0IC b F186h E C3h CAN Module Interrupt Control Register 0000h XP1IC b F18Eh E C7h X-Peripheral 1 Interrupt Control Register 0000h XP2IC b F196h E CBh X-Peripheral 2 Interrupt Control Register 0000h XP3IC b F19Eh E CFh PLL Interrupt Control Register 0000h ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h Table 19.1 Special Function Register List (cont’d) Name Physical Address 8-Bit Address Description Reset Value 3 |
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