ST10F167 datasheet(31/69 Pages) STMICROELECTRONICS

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ST10F167

PARALLEL PORTS

The ST10F167 provides up to 77 I/O lines which

are organized into eight input/output ports and one

input port. All port lines are bit-addressable, and all

input/output lines are individually (bit-wise) pro-

grammable as inputs or outputs via direction regis-

ters. The I/O ports are true bidirectional ports

which are switched to high impedance state when

configured as inputs. The output drivers of three I/

O ports can be configured (pin by pin) for push/pull

operation or open-drain operation via control reg-

isters. During the internal reset, all port pins are

configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and

Port 8 is selectable (TTL or CMOS like). The spe-

cial CMOS like input threshold reduces noise sen-

sitivity due to the input hysteresis. The input

threshold may be selected individually for each

byte of the respective ports.

All port lines have programmable alternate input or

output functions associated with them. PORT0

and PORT1 may be used as address and data

lines when accessing external memory, while Port

4 outputs the additional segment address bits A23/

19/17...A16 in systems where segmentation is en-

abled to access more than 64KBytes of memo-

ry.Port 2, Port 8 and Port 7 are associated with the

capture inputs or compare outputs of the CAP-

COM units and/or with the outputs of the PWM

module. Port 6 provides optional bus arbitration

signals (BREQ, HLDA, HOLD) and chip select sig-

nals. Port 3 includes alternate functions of timers,

serial interfaces, the optional bus control signal

BHE and the system clock output (CLKOUT).

Port 5 is used for the analog input channels to the

A/D converter or timer control signals.

All port lines that are not used for these alternate

functions may be used as general purpose IO

lines.

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