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ST10F167 数据表(PDF) 51 Page - STMicroelectronics

部件名 ST10F167
功能描述  16-BIT MCU WITH 128K BYTE FLASH MEMORY
PDF  69 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F167 数据表(HTML) 51 Page - STMicroelectronics

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ST10F167
20.5.7 Multiplexed Bus
VDD =5 V ± 5%,VSS =0 V, TA = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF,CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2
t
A + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Table 20.6
Multiplexed Bus Characteristics
Parameter
Symbol
Max. CPU Clock
=20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
ALE high time
t5 CC
15 +
t
A
–TCL - 10 +
t
A
–ns
Address setup to ALE
t6 CC
0 +
t
A
–TCL - 25 +
t
A
–ns
Address hold after ALE
t7 CC
15 +
t
A
–TCL - 10 +
t
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
t8 CC
15 +
t
A
–TCL - 10 +
t
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
t9 CC
-10 +
t
A
–
-10 +
t
A
–ns
Address float after RD, WR
(with RW-delay)
t10 CC
–
5
–
5
ns
Address float after RD, WR
(no RW-delay)
t11 CC
–
30
–
TCL + 5
ns
RD, WR low time
(with RW-delay)
t
12 CC
25 +
t
C
–
2TCL - 25
+
t
C
–ns
RD, WR low time
(no RW-delay)
t
13 CC
65 +
t
C
–
3TCL - 10
+
t
C
–ns
RD to valid data in
(with RW-delay)
t
14 SR
–
5 +
t
C
–
2TCL - 45
+
t
C
ns
RD to valid data in
(no RW-delay)
t
15 SR
–
55 +
t
C
–
3TCL - 20
+
t
C
ns
ALE low to valid data in
t
16 SR
–
40 +
t
A + tC
–
3TCL - 35
+
t
A + tC
ns
Address to valid data in
t17 SR
–
60
+2
t
A + tC
–
4TCL - 40
+2
t
A + tC
ns
Data hold after RD
rising edge
t
18 SR
0
–
0
–
ns
Data float after RD
t
19 SR
–
35 +
t
F
–
2TCL - 15 +
t
F
ns
Data valid to WR
t
22 SR
15 +
t
C
–
2TCL - 35
+
t
C
–ns
Data hold after WR
t
23 CC
35 +
t
F
–
2TCL - 15
+
t
F
–ns
ALE rising edge after RD,
WR
t
25 CC
35 +
t
F
–
2TCL - 15
+
t
F
–ns
Address hold after RD, WR
t
27 CC
35 +
t
F
–
2TCL - 15 +
t
F
–ns
3



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