ST10F167 datasheet(15/69 Pages) STMICROELECTRONICS

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ST10F167

6.2

Flash Control Register (FCR)

In the standard operation mode, the FLASH mem-

ory can be accessed in the same way as the nor-

mal mask-programmable on-chip ROM. All, appro-

priate, direct and indirect addressing modes can

be used for reading the FLASH memory.

All programming or erase operations are control-

led via a 16-bit register, the FCR. The FCR is not

an SFR or GPR. To prevent inadvertent writing to

the FLASH memory, the FCR is locked and inac-

tive during the standard operation mode. The

FLASH memory writing mode must be entered,

before a valid access to the FCR is provided. This

is done via a special key code instruction se-

quence.

The FCR is virtually mapped into the active ad-

dress space of the Flash memory. It can only be

accessed with direct 16-bit (mem) addressing

modes. Since the FCR is neither byte, nor bit-ad-

dressable, only word operand instructions can be

used for FCR accesses. By default, the FCR can

be accessed with any even address from 000000h

to 07FFFEh and 018000h to 02FFFEh. If the first

32K byte Block of the FLASH memory is mapped

to segment 1, the corresponding even FCR ad-

dresses are 010000h to 017FFEh. Note that DPP

referencing and DPP contents must be considered

for FCR accesses. If an FCR access is attempted

via an odd address, an illegal operand access

hardware trap will occur.

FCR

Flash Control Register

Reset Condition: 0000h (Read)

b15 = FWMSET:

Flash Writing Mode Set. This bit

is set to ”1” automatically once the Flash writing

mode is entered. To exit from the Flash writing

mode, FWMSET must be set to ”0”. Since only

word values can be written to FCR, care must be

taken that FWMSET is not cleared inadvertently.

Therefore, for any command written to FCR (ex-

cept for the return to the Flash standard mode),

FWMSET must be set to ”1”. Reset condition of

FWMSET is ”0”.

b14-b10 = Reserved: these bits are reserved for

future development, they must be written to ”0”.

b9-b8 = BE0,1:

Bank erase select. These bits se-

lect the Flash memory bank to be erased. The

physical addresses of bank 0 depends on the

which Flash memory map has been chosen. In

Flash operating modes, other than the erasing

mode, these bits are not significant. At reset BE1,0

are set to ”00”.

b7 = WDWW:

Word/double word write. This bit de-

termines the word width used for programming op-

erations: 16-bit (WDWW = 0) or 32-bit (WDWW =

”1”). In Flash operation modes, other than the pro-

gramming mode, this bit is not significant. At reset,

WDWW is set to “0”.

b6-b5 = CKCTL0,1:

Flash Timer Clock Control.

These two bits control the width (TPRG) of the pro-

gramming or erase pulses applied to the Flash

memory cells during the operation. TPRG varies in

an inverse ratio to the clock frequency. To avoid

putting the Flash memory under critical stress con-

ditions, the width of one single programming or

erase pulse and the programming or erase time,

must not exceed defined values. Thus the maxi-

mum number of programming or erase attempts,

depends on the system clock frequency.

RESET state: 00.

b4 = VPPRIV:

PP Revelation bit. This read-only bit

reflects the state of the V

PP voltage in the Flash

writing mode. If VPPRIV is set to ”0”, this indicates

that VPP is below the threshold necessary for relia-

ble programming. The normal reaction to this indi-

cation is to check the V

PP power supply and to then

repeat the intended operation. If the V

PP voltage is

above a sufficient margin, VPPRIV will be set to

”1”. The reset state of the VPPRIV bit depends on

the state of the external V

PP voltage at the VPP pin.

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