ST92F120JR9T datasheet(108/320 Pages) STMICROELECTRONICS

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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK CONTROL REGISTERS (Cont’d)

PLL CONFIGURATION REGISTER (PLLCONF)

R246 - Read/Write

Reset Value: xx00x111 (xxh)

Bit 5:4 = MX[1:0]:

PLL Multiplication Factor.

Refer to Table 22 for multiplier settings.

WARNING: After these bits are modified, take

care that the PLL lock-in time has elapsed before

setting the CSU_CKSEL bit in the CLK_FLAG reg-

ister.

Bit 2:0 = DX[2:0]:

PLL output clock divider factor.

Refer to Table 23 for divider settings.

Figure 50. RCCU General Timing

MX1

MX0

DX2

DX1

DX0

Table 22. PLL Multiplication Factors

MX1

MX0

CLOCK2 x

Table 23. PLL Divider Factors

DX2

DX1

DX0

PLL CLOCK/1

PLL CLOCK/2

PLL CLOCK/3

PLL CLOCK/4

PLL CLOCK/5

PLL CLOCK/6

PLL CLOCK/7

CLOCK2

(PLL OFF, Reset State)

PLL Multiplier

CLOCK2

INTCLK

Internal

Reset

Clock

PLL switched on by user

TRSPH

PLL Lock-in Time

Exit from RESET

PLL selected by user

Boot ROM execution

User program execution

Reset phase

Internal

Reset

RESET

µs

VR02113B

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