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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

7.6 RESET/STOP MANAGER

The Reset/Stop Manager resets the MCU when

one of the three following events occurs:

– A Hardware reset, initiated by a low level on the

Reset pin.

– A Software reset, initiated by a HALT instruction

(when enabled).

– A Watchdog end of count condition.

The event which caused the last Reset is flagged

in the CLK_FLAG register, by setting the SOF-

TRES or the WDGRES bits respectively; a hard-

ware initiated reset will leave both these bits reset.

The hardware reset overrides all other conditions

and forces the ST9 to the reset state. During Re-

set, the internal registers are set to their reset val-

ues (when these reset values are defined, other-

wise the register content will remain unchanged),

and the I/O pins are set to Bidirectional Weak-Pull-

Up or High impedance input. See Section 1.3.

Reset is asynchronous: as soon as the reset pin is

driven low, a Reset cycle is initiated.

Figure 55. Oscillator Start-up Sequence and Reset Timing

VDD MAX

VDD MIN

OSCIN

INTCLK

RESET

TSTUP

VR02085A

Note: For TSTUP value refer to Oscillator Electrical Characteristics

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