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ST92F120JR9T 数据表(PDF) 114 Page - STMicroelectronics |
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ST92F120JR9T 数据表(HTML) 114 Page - STMicroelectronics |
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114 / 320 page  114/320 ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) 8 EXTERNAL MEMORY INTERFACE (EXTMI) 8.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 Page 0. If the two registers EMR1 and EMR2 are set to the proper values, the ST9+ memory access cycle is similar to that of the original ST9, with the only ex- ception that it is composed of just two system clock phases, named T1 and T2. During phase T1, the memory address is output on the AS falling edge and is valid on the rising edge of AS. Port0 and Port 1 maintain the address sta- ble until the following T1 phase. During phase T2, two forms of behavior are possi- ble. If the memory access is a Read cycle, Port 0 pins are released in high-impedance until the next T1 phase and the data signals are sampled by the ST9 on the rising edge of DS. If the memory ac- cess is a Write cycle, on the falling edge of DS, Port 0 outputs data to be written in the external memory. Those data signals are valid on the rising edge of DS and are maintained stable until the next address is output. Note that DS is pulled low at the beginning of phase T2 only during an exter- nal memory access. Figure 57. Page 21 Registers n DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h MMU EXT.MEM Page 21 MMU Bit DPRREM=0 SSPL SSPH USPL USPH MODER PPR RP1 RP0 FLAGR CICR P5 P4 P3 P2 P1 P0 DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 Bit DPRREM=1 SSPL SSPH USPL USPH MODER PPR RP1 RP0 FLAGR CICR P5 P4 P3 P2 P1 P0 DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 Relocation of P[3:0] and DPR[3:0] Registers 9 |
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