ST92F120JR9T datasheet(146/320 Pages) STMICROELECTRONICS

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EXTENDED FUNCTION TIMER (EFT)

EXTENDED FUNCTION TIMER (Cont’d)

10.3.3.4 Output Compare

In this section, the index,

i, may be 1 or 2.

This function can be used to control an output

waveform or indicating when a period of time has

elapsed.

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

iE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the free run-

ning counter each timer clock cycle.

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

Timing resolution is one count of the free running

counter: (INTCLK/CC[1:0]).

Procedure

To use the output compare function, select the fol-

lowing in the CR2 register:

– Set the OC

iE bit if an output is needed then the

OCMP

i pin is dedicated to the output compare i

function.

– Select the timer clock CC[1:0] (see Table 29).

And select the following in the CR1 register:

– Select the OLVL

i bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE and OCIS bits (or EFTIS bit if only

global interrupt is available) to generate an inter-

rupt if it is needed.

When match is found:

– OCF

i bit is set.

– The OCMP

i pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset and stays low

until valid compares change it to OLVL

i level).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and OCIS bit (or EFTIS bit

if only global interrupt is available) is set in the

CR3 register.

Clearing the output compare interrupt request is

done by:

3. Reading the SR register while the OCF

i bit is

set.

4. An access (read or write) to the OC

iLR register.

Note: After a processor write cycle to the OC

iHR

until the OC

iLR register is also written.

If the OC

iE bit is not set, the OCMPi pin is a gen-

eral I/O port and the OLVL

i bit will not appear

when match is found but an interrupt could be gen-

erated if the OCIE bit is set.

The value in the 16-bit OCiR register and the

OLVL

i bit should be changed after each success-

ful comparison in order to control an output wave-

form or establish a new elapsed timeout.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

∆t

= Desired output compare period (in

seconds)

INTCLK

= Internal clock frequency

CC1-CC0 = Timer clock prescaler

The following procedure is recommended to pre-

vent the OCF

i bit from being set between the time

it is read and the write to the OCiR register:

– Write to the OC

iHR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

i bit, which may be already set).

– Write to the OC

iLR register (enables the output

compare function and clears the OCF

i bit).

MS Byte

LS Byte

iROCiHR

iLR

∆ OCiR= ∆

t * INTCLK

(CC1.CC0)

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